1. Field of the Invention
The present invention relates to an on-chip network interfacing apparatus and method, and more particularly, to an on-chip network interfacing apparatus that includes an interface circuit that establishes communications among modules designed according to an advanced microcontroller bus architecture (hereinafter, referred to as “AMBA”) 2.0 on-chip bus protocol and an on-chip network device designed according to an on-chip network protocol, and a method therefor.
2. Description of the Related Art
In general, the AMBA 2.0 on-chip bus protocol is often used to establish communications between on-chip circuits. FIG. 1 is a block diagram illustrating the structure of a conventional AMBA 2.0 on-chip bus that is designed according to the AMBA 2.0 on-chip bus protocol. Referring to FIG. 1, the AMBA 2.0 on-chip bus allows a master module 110 to communicate with a slave module 120. The master module 110 includes first through third master modules 111 through 113, and the slave module 120 includes first through fourth slave modules 121 through 124. Here, the master module 110 is a module that requests data for communications and the slave module 120 is a module that is requested to provide the communications data. Thus, the master module 110 transmits only read/write request signals, and the slave module 120 transmits read data/write data in response to the read/write request signals.
The AMBA 2.0 on-chip bus of FIG. 1 includes an arbiter 130, a decoder 140, a read data multiplexer 170 that allows the master module 110 to request the read data and the slave module 120 to transmit the read data, a write data multiplexer 160 that allows the master module 110 to request the write data and the slave module 120 to transmit the write data, and an address and control multiplexer 150 that allows the master module 110 to transmit control/address information to the slave module 120.
The master module 110 transmits a request signal for use of the AMBA 2.0 on-chip bus to the arbiter 130.
The arbiter 130 sets an order in which the AMBA 2.0 on-chip bus is to be used by the modules of the master module 110. Request signals output from the modules of the master module 110 are connected to a plurality of input terminals of the arbiter 130, and thus, the arbiter 130 sequentially receives the request signals in a set order. The arbiter 130 gives priority over use of the AMBA 2.0 on-chip bus to the modules of the master module 110 according to the set order. The master module that acquires a right of the AMBA 2.0 on-chip bus, communicates with one of the modules of the slave module 120 via the address and control multiplexer 150 and the read data multiplexer 170, or via the address and control multiplexer 150 and the write data multiplexer 160. The slave module to be communicated with is determined by the decoder 140.
However, the AMBA 2.0 on-chip bus experiences a bandwidth limitation when exchanging data between the master module 110 and the slave module 120, which is caused due to physical sharing of a wire. When a physical bus is occupied by a master module, the other master modules cannot establish communications in the AMBA 2.0 on-chip bus.
To solve these problems, an on-chip network protocol will be described in greater detail with reference to FIG. 2.
FIG. 2 is a block diagram of a conventional on-chip network apparatus designed according to an on-chip network protocol. Referring to FIG. 2, the on-chip network apparatus includes a plurality of first on-chip network ports 210, and a switch 220. Each of the first on-chip network ports 210 includes an up sampler 212 that transmits on-chip network signals received from a plurality of first modules 250, which are designed according to the on-chip network protocol, to the switch 220 in the order that the on-chip network signals were received; and a down sampler 214 that transmits the on-chip network signals received from the switch 220 to the first modules 250 in the reverse order that the on-chip network signals were received. The on-chip network apparatus of FIG. 2 is designed to solve a problem that a master module has to wait when a grant for use of an AMBA 2.0 on-chip bus is given to another master module. Specifically, when there are many master modules that simultaneously request use of the AMBA 2.0 on-chip bus to communicate with different slave modules, the on-chip network apparatus of FIG. 2 allows the master modules to simultaneously communicate without waiting for a grant for use of the bus. Even if they want to communicate with the same slave module, the on-chip network apparatus of FIG. 2 makes it possible by dividing desired data into predetermined units.
The switch 220 is a physical medium that delivers a signal, which is transmitted to the first module 250 from the first on-chip network ports 210, to a plurality of second on-chip network ports 210′.
In the on-chip network apparatus of FIG. 2, even while the first module 250 uses a network, a plurality of second on-chip network ports 250′ can use the network without requesting use of the network and waiting for a grant for use. This is because data is transmitted in packet units. That is, since the first and second modules 250 and 250′ are connected to the switch 220, which collects packets and send them to a target destination, via different media, data from the first modules 250 is transmitted to the network in packet units irrespective of the amount of the data. Also, each packet to be transmitted contains a tag that specifies a destination, a departure place, and the characteristics of the packet. Accordingly, even if packets generated by different systems are mixed, it is possible to sequentially transmit the packets to their target destinations by decoding the tags contained in the packets. The switch 220 decodes the tags contained in packets and sequentially transmits the packets to their destinations.
The construction of the switch 220 will now be described in greater detail with reference to FIG. 3. FIG. 3 is a detailed block diagram of the switch 220 illustrated in FIG. 2. Referring to FIG. 3, the switch 220 includes a plurality of in-ports 222, a plurality of arbiters 224, and a switch fabric 226.
Each of the in-ports 222 queues incoming data from a corresponding arbiter 224 and transmits a request signal for use of the switch fabric 226 to the corresponding arbiter 224. The arbiter 224 receives the request signal from the in-port 222 and transmits a signal granting the use of the switch fabric 226 to the in-port 222. The switch fabric 226 outputs the data received via the in-port 222.
More specifically, the switch 220 receives packets, which are to be transmitted to different destinations, via the in-ports 222. The received packets are sent to their destinations via the switch fabric 226. Each of in-ports 222 is connected to all of the destinations via the switch fabric 226. The in-port 222 decodes a tag from a packet and sends a request signal for use of the switch fabric 226 to the arbiter 224. When the switch fabric 226 is unoccupied, the arbiter 224 accepts the request for use of the switch fabric 226 and sends the packet stored in the in-port 222 to the switch fabric 226. Accordingly, it is possible to simultaneously transmit packets corresponding to the arbiters 224 to the destinations of the packets. However, while the arbiter 224 is in use, the packets are queued in the in-port 222. In this case, until a master module completes all desired operations, the packets stand by in the in-ports 222 similar to a bus but the number of the packets is less than that of packets that stand by to receive a grant for use of the bus. However, since most conventional modules are designed according to the AMBA 2.0 on-chip bus protocol, an interface circuit must be installed between each conventional module and an on-chip network so as to establish communications via the on-chip network.